Commit f3a01cb0 authored by Thomas Petazzoni's avatar Thomas Petazzoni
Browse files

Add x86_64 variants to BR2_GCC_TARGET_ARCH 



With the Sourcery CodeBench IA32/AMD64 toolchain, the proper -march=
switch must be passed. So, on x86_64, we make sure that
BR2_GCC_TARGET_ARCH gets defined to the correct value, just as we do
on x86.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
parent dca6e03e

target/Config.in.arch

+5 −0
Original line number Diff line number Diff line
@@ -678,6 +678,11 @@ config BR2_GCC_TARGET_ARCH 
	default athlon-4	if BR2_x86_athlon_4

	default winchip-c6	if BR2_x86_winchip_c6

	default winchip2	if BR2_x86_winchip2

	default nocona		if BR2_x86_64_nocona

	default core2		if BR2_x86_64_core2

	default k8		if BR2_x86_64_opteron

	default k8-sse3		if BR2_x86_64_opteron_sse3

	default barcelona	if BR2_x86_64_barcelona

	default c3		if BR2_x86_c3

	default c3-2		if BR2_x86_c32

	default geode		if BR2_x86_geode