Commit 79ee3c1f authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Peter Korsgaard
Browse files

Split target/Config.in.arch into multiple Config.in.* in arch/ 



target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:

 * An initial Config.in that lists the top-level architecture, and
   sources the arch-specific Config.in.<arch> files, as well as
   Config.in.common (see below)

 * One Config.in.<arch> per architecture, listing the CPU families,
   ABI choices, etc.

 * One Config.in.common that defines the gcc mtune, march, mcpu values
   and other hidden options.

[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarPeter Korsgaard <jacmet@sunsite.dk>
parent 6c3e3ad4

Config.in

+1 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ config BR2_HOSTARCH 
	string

	option env="HOSTARCH"



source "target/Config.in.arch"

source "arch/Config.in"



menu "Build options"

arch/Config.in

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config BR2_ARCH_IS_64

       bool



choice

	prompt "Target Architecture"

	default BR2_i386

	help

	  Select the target architecture family to build for.



config BR2_arm

	bool "ARM (little endian)"

	help

	  ARM is a 32-bit reduced instruction set computer (RISC) instruction

	  set architecture (ISA) developed by ARM Holdings. Little endian.

	  http://www.arm.com/

	  http://en.wikipedia.org/wiki/ARM



config BR2_armeb

	bool "ARM (big endian)"

	help

	  ARM is a 32-bit reduced instruction set computer (RISC) instruction

	  set architecture (ISA) developed by ARM Holdings. Big endian.

	  http://www.arm.com/

	  http://en.wikipedia.org/wiki/ARM



config BR2_aarch64

	bool "AArch64"

	help

	  Aarch64 is a 64-bit architecture developed by ARM Holdings.

	  http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php

	  http://en.wikipedia.org/wiki/ARM



config BR2_avr32

	bool "AVR32"

	select BR2_SOFT_FLOAT

	help

	  The AVR32 is a 32-bit RISC microprocessor architecture designed by

	  Atmel.

	  http://www.atmel.com/

	  http://en.wikipedia.org/wiki/Avr32



config BR2_bfin

	bool "Blackfin"

	help

	  The Blackfin is a family of 16 or 32-bit microprocessors developed,

	  manufactured and marketed by Analog Devices.

	  http://www.analog.com/

	  http://en.wikipedia.org/wiki/Blackfin



config BR2_i386

	bool "i386"

	help

	  Intel i386 architecture compatible microprocessor

	  http://en.wikipedia.org/wiki/I386



config BR2_m68k

	bool "m68k"

	depends on BROKEN # ice in uclibc / inet_ntoa_r

	help

	  Motorola 68000 family microprocessor

	  http://en.wikipedia.org/wiki/M68k



config BR2_microblazeel

	bool "Microblaze AXI (little endian)"

	help

	  Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus

	  based architecture (little endian)

	  http://www.xilinx.com

	  http://en.wikipedia.org/wiki/Microblaze



config BR2_microblazebe

	bool "Microblaze non-AXI (big endian)"

	help

	  Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus

	  based architecture (non-AXI, big endian)

	  http://www.xilinx.com

	  http://en.wikipedia.org/wiki/Microblaze



config BR2_mips

	bool "MIPS (big endian)"

	help

	  MIPS is a RISC microprocessor from MIPS Technologies. Big endian.

	  http://www.mips.com/

	  http://en.wikipedia.org/wiki/MIPS_Technologies



config BR2_mipsel

	bool "MIPS (little endian)"

	help

	  MIPS is a RISC microprocessor from MIPS Technologies. Little endian.

	  http://www.mips.com/

	  http://en.wikipedia.org/wiki/MIPS_Technologies



config BR2_mips64

	bool "MIPS64 (big endian)"

	select BR2_ARCH_IS_64

	help

	  MIPS is a RISC microprocessor from MIPS Technologies. Big endian.

	  http://www.mips.com/

	  http://en.wikipedia.org/wiki/MIPS_Technologies



config BR2_mips64el

	bool "MIPS64 (little endian)"

	select BR2_ARCH_IS_64

	help

	  MIPS is a RISC microprocessor from MIPS Technologies. Little endian.

	  http://www.mips.com/

	  http://en.wikipedia.org/wiki/MIPS_Technologies



config BR2_powerpc

	bool "PowerPC"

	help

	  PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.

	  http://www.power.org/

	  http://en.wikipedia.org/wiki/Powerpc



config BR2_sh

	bool "SuperH"

	help

	  SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)

	  instruction set architecture (ISA) developed by Hitachi.

	  http://www.hitachi.com/

	  http://en.wikipedia.org/wiki/SuperH



config BR2_sh64

	bool "SuperH64"

	help

	  SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)

	  instruction set architecture (ISA) developed by Hitachi.

	  http://www.hitachi.com/

	  http://en.wikipedia.org/wiki/SuperH



config BR2_sparc

	bool "SPARC"

	help

	  SPARC (from Scalable Processor Architecture) is a RISC instruction

	  set architecture (ISA) developed by Sun Microsystems.

	  http://www.oracle.com/sun

	  http://en.wikipedia.org/wiki/Sparc



config BR2_x86_64

	bool "x86_64"

	select BR2_ARCH_IS_64

	help

	  x86-64 is an extension of the x86 instruction set (Intel i386

	  architecture compatible microprocessor).

	  http://en.wikipedia.org/wiki/X86_64



endchoice



config BR2_microblaze

	bool

	default y if BR2_microblazeel || BR2_microblazebe



source "arch/Config.in.arm"

source "arch/Config.in.bfin"

source "arch/Config.in.mips"

source "arch/Config.in.powerpc"

source "arch/Config.in.sh"

source "arch/Config.in.sparc"

source "arch/Config.in.x86"

source "arch/Config.in.common"

arch/Config.in.arm

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choice

	prompt "Target Architecture Variant"

	depends on BR2_arm || BR2_armeb

	default BR2_generic_arm

	help

	  Specific CPU variant to use



config BR2_generic_arm

	bool "generic_arm"

config BR2_arm7tdmi

	bool "arm7tdmi"

config BR2_arm610

	bool "arm610"

config BR2_arm710

	bool "arm710"

config BR2_arm720t

	bool "arm720t"

config BR2_arm920t

	bool "arm920t"

config BR2_arm922t

	bool "arm922t"

config BR2_arm926t

	bool "arm926t"

config BR2_arm10t

	bool "arm10t"

config BR2_arm1136jf_s

	bool "arm1136jf_s"

config BR2_arm1176jz_s

	bool "arm1176jz-s"

config BR2_arm1176jzf_s

	bool "arm1176jzf-s"

config BR2_cortex_a8

	bool "cortex-A8"

config BR2_cortex_a9

	bool "cortex-A9"

config BR2_sa110

	bool "sa110"

config BR2_sa1100

	bool "sa1100"

config BR2_xscale

	bool "xscale"

config BR2_iwmmxt

	bool "iwmmxt"

endchoice



choice

	prompt "Target ABI"

	depends on BR2_arm || BR2_armeb

	default BR2_ARM_EABI

	help

	  Application Binary Interface to use



	  Note:

	    Using OABI is discouraged.



config BR2_ARM_EABI

	bool "EABI"

config BR2_ARM_OABI

	bool "OABI"

	depends on !BR2_GCC_VERSION_4_7_X

endchoice

arch/Config.in.bfin

0 → 100644
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choice

	prompt "Target ABI"

	depends on BR2_bfin

	default BR2_BFIN_FDPIC

config BR2_BFIN_FDPIC

	bool "FDPIC"

config BR2_BFIN_FLAT

	bool "FLAT"

	select BR2_PREFER_STATIC_LIB

endchoice

target/Config.in.arch→arch/Config.in.common

+245 −0
Original line number Diff line number Diff line 
config BR2_ARCH_IS_64

       bool



choice

	prompt "Target Architecture"

	default BR2_i386

	help

	  Select the target architecture family to build for.



config BR2_arm

	bool "ARM (little endian)"

	help

	  ARM is a 32-bit reduced instruction set computer (RISC) instruction

	  set architecture (ISA) developed by ARM Holdings. Little endian.

	  http://www.arm.com/

	  http://en.wikipedia.org/wiki/ARM



config BR2_armeb

	bool "ARM (big endian)"

	help

	  ARM is a 32-bit reduced instruction set computer (RISC) instruction

	  set architecture (ISA) developed by ARM Holdings. Big endian.

	  http://www.arm.com/

	  http://en.wikipedia.org/wiki/ARM



config BR2_aarch64

	bool "AArch64"

	help

	  Aarch64 is a 64-bit architecture developed by ARM Holdings.

	  http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php

	  http://en.wikipedia.org/wiki/ARM



config BR2_avr32

	bool "AVR32"

	select BR2_SOFT_FLOAT

	help

	  The AVR32 is a 32-bit RISC microprocessor architecture designed by

	  Atmel.

	  http://www.atmel.com/

	  http://en.wikipedia.org/wiki/Avr32



config BR2_bfin

	bool "Blackfin"

	help

	  The Blackfin is a family of 16 or 32-bit microprocessors developed,

	  manufactured and marketed by Analog Devices.

	  http://www.analog.com/

	  http://en.wikipedia.org/wiki/Blackfin



config BR2_i386

	bool "i386"

	help

	  Intel i386 architecture compatible microprocessor

	  http://en.wikipedia.org/wiki/I386



config BR2_m68k

	bool "m68k"

	depends on BROKEN # ice in uclibc / inet_ntoa_r

	help

	  Motorola 68000 family microprocessor

	  http://en.wikipedia.org/wiki/M68k



config BR2_microblazeel

	bool "Microblaze AXI (little endian)"

	help

	  Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus

	  based architecture (little endian)

	  http://www.xilinx.com

	  http://en.wikipedia.org/wiki/Microblaze



config BR2_microblazebe

	bool "Microblaze non-AXI (big endian)"

	help

	  Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus

	  based architecture (non-AXI, big endian)

	  http://www.xilinx.com

	  http://en.wikipedia.org/wiki/Microblaze



config BR2_mips

	bool "MIPS (big endian)"

	help

	  MIPS is a RISC microprocessor from MIPS Technologies. Big endian.

	  http://www.mips.com/

	  http://en.wikipedia.org/wiki/MIPS_Technologies



config BR2_mipsel

	bool "MIPS (little endian)"

	help

	  MIPS is a RISC microprocessor from MIPS Technologies. Little endian.

	  http://www.mips.com/

	  http://en.wikipedia.org/wiki/MIPS_Technologies



config BR2_mips64

	bool "MIPS64 (big endian)"

	select BR2_ARCH_IS_64

	help

	  MIPS is a RISC microprocessor from MIPS Technologies. Big endian.

	  http://www.mips.com/

	  http://en.wikipedia.org/wiki/MIPS_Technologies



config BR2_mips64el

	bool "MIPS64 (little endian)"

	select BR2_ARCH_IS_64

	help

	  MIPS is a RISC microprocessor from MIPS Technologies. Big endian.

	  http://www.mips.com/

	  http://en.wikipedia.org/wiki/MIPS_Technologies



config BR2_powerpc

	bool "PowerPC"

	help

	  PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.

	  http://www.power.org/

	  http://en.wikipedia.org/wiki/Powerpc



config BR2_sh

	bool "SuperH"

	help

	  SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)

	  instruction set architecture (ISA) developed by Hitachi.

	  http://www.hitachi.com/

	  http://en.wikipedia.org/wiki/SuperH



config BR2_sh64

	bool "SuperH64"

	help

	  SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)

	  instruction set architecture (ISA) developed by Hitachi.

	  http://www.hitachi.com/

	  http://en.wikipedia.org/wiki/SuperH



config BR2_sparc

	bool "SPARC"

	help

	  SPARC (from Scalable Processor Architecture) is a RISC instruction

	  set architecture (ISA) developed by Sun Microsystems.

	  http://www.oracle.com/sun

	  http://en.wikipedia.org/wiki/Sparc



config BR2_x86_64

	bool "x86_64"

	select BR2_ARCH_IS_64

	help

	  x86-64 is an extension of the x86 instruction set (Intel i386

	  architecture compatible microprocessor).

	  http://en.wikipedia.org/wiki/X86_64



endchoice



config BR2_microblaze

	bool

	default y if BR2_microblazeel || BR2_microblazebe



#

# Keep the variants separate, there's no need to clutter everything else.

# sh is fairly "special" in this regard, as virtually everyone else has

# things kept down to a _sensible_ number of target variants. No such

# luck for sh..

#

choice

	prompt "Target Architecture Variant"

	depends on BR2_arm || BR2_armeb

	default BR2_generic_arm

	help

	  Specific CPU variant to use



config BR2_generic_arm

	bool "generic_arm"

config BR2_arm7tdmi

	bool "arm7tdmi"

config BR2_arm610

	bool "arm610"

config BR2_arm710

	bool "arm710"

config BR2_arm720t

	bool "arm720t"

config BR2_arm920t

	bool "arm920t"

config BR2_arm922t

	bool "arm922t"

config BR2_arm926t

	bool "arm926t"

config BR2_arm10t

	bool "arm10t"

config BR2_arm1136jf_s

	bool "arm1136jf_s"

config BR2_arm1176jz_s

	bool "arm1176jz-s"

config BR2_arm1176jzf_s

	bool "arm1176jzf-s"

config BR2_cortex_a8

	bool "cortex-A8"

config BR2_cortex_a9

	bool "cortex-A9"

config BR2_sa110

	bool "sa110"

config BR2_sa1100

	bool "sa1100"

config BR2_xscale

	bool "xscale"

config BR2_iwmmxt

	bool "iwmmxt"

endchoice



choice

	prompt "Target ABI"

	depends on BR2_arm || BR2_armeb

	default BR2_ARM_EABI

	help

	  Application Binary Interface to use



	  Note:

	    Using OABI is discouraged.



config BR2_ARM_EABI

	bool "EABI"

config BR2_ARM_OABI

	bool "OABI"

	depends on !BR2_GCC_VERSION_4_7_X

endchoice



choice

	prompt "Target ABI"

	depends on BR2_bfin

	default BR2_BFIN_FDPIC

config BR2_BFIN_FDPIC

	bool "FDPIC"

config BR2_BFIN_FLAT

	bool "FLAT"

	select BR2_PREFER_STATIC_LIB

endchoice



choice

	prompt "Target Architecture Variant"

	depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el

	default BR2_mips_3 if BR2_mips

	default BR2_mips_1 if BR2_mipsel

	default BR2_mips_64 if BR2_mips64 || BR2_mips64el

	help

	  Specific CPU variant to use



	  64bit cabable: 3, 4, 64, 64r2

	  non-64bit capable: 1, 2, 32, 32r2



config BR2_mips_1

	bool "mips I (generic)"

	depends on !BR2_ARCH_IS_64

config BR2_mips_2

	bool "mips II"

	depends on !BR2_ARCH_IS_64

config BR2_mips_3

	bool "mips III"

config BR2_mips_4

	bool "mips IV"

config BR2_mips_32

	bool "mips 32"

	depends on !BR2_ARCH_IS_64

config BR2_mips_32r2

	bool "mips 32r2"

	depends on !BR2_ARCH_IS_64

config BR2_mips_64

	bool "mips 64"

config BR2_mips_64r2

	bool "mips 64r2"

endchoice





choice

	prompt "Target ABI"

	depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el

	default BR2_MIPS_OABI32 if !BR2_ARCH_IS_64

	default BR2_MIPS_NABI32 if BR2_ARCH_IS_64

	help

	  Application Binary Interface to use



config BR2_MIPS_OABI32

	bool "o32"

config BR2_MIPS_NABI32

	bool "n32"

	depends on BR2_ARCH_IS_64

config BR2_MIPS_NABI64

	bool "n64"

	depends on BR2_ARCH_IS_64

endchoice



choice

	prompt "Target Architecture Variant"

	depends on BR2_sh

	default BR2_sh4

	help

	  Specific CPU variant to use



config BR2_sh2

	bool "sh2 (SH2 big endian)"

config BR2_sh2a

	bool "sh2a (SH2A big endian)"

config BR2_sh3

	bool "sh3 (SH3 little endian)"

config BR2_sh3eb

	bool "sh3eb (SH3 big endian)"

config BR2_sh4

	bool "sh4 (SH4 little endian)"

config BR2_sh4eb

	bool "sh4eb (SH4 big endian)"

config BR2_sh4a

	bool "sh4a (SH4A little endian)"

config BR2_sh4aeb

	bool "sh4aeb (SH4A big endian)"

endchoice



#

# gcc builds libstdc++ differently depending on the

# host tuplet given to it, so let people choose

#



# i386/x86_64 cpu features

config BR2_X86_CPU_HAS_MMX

	bool

config BR2_X86_CPU_HAS_SSE

	bool

config BR2_X86_CPU_HAS_SSE2

	bool

config BR2_X86_CPU_HAS_SSE3

	bool

config BR2_X86_CPU_HAS_SSSE3

	bool



choice

	prompt "Target Architecture Variant"

	depends on BR2_i386 || BR2_x86_64

	default BR2_x86_i586 if BR2_i386

	default BR2_x86_generic if BR2_x86_64

	help

	  Specific CPU variant to use



config BR2_x86_generic

	bool "generic"

config BR2_x86_i386

	bool "i386"

	depends on !BR2_x86_64

config BR2_x86_i486

	bool "i486"

	depends on !BR2_x86_64

config BR2_x86_i586

	bool "i586"

	depends on !BR2_x86_64

config BR2_x86_i686

	bool "i686"

	depends on !BR2_x86_64

config BR2_x86_pentiumpro

	bool "pentium pro"

	depends on !BR2_x86_64

config BR2_x86_pentium_mmx

	bool "pentium MMX"

	select BR2_X86_CPU_HAS_MMX

	depends on !BR2_x86_64

config BR2_x86_pentium_m

	bool "pentium mobile"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	depends on !BR2_x86_64

config BR2_x86_pentium2

	bool "pentium2"

	select BR2_X86_CPU_HAS_MMX

	depends on !BR2_x86_64

config BR2_x86_pentium3

	bool "pentium3"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	depends on !BR2_x86_64

config BR2_x86_pentium4

	bool "pentium4"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	select BR2_X86_CPU_HAS_SSE2

	depends on !BR2_x86_64

config BR2_x86_prescott

	bool "prescott"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	select BR2_X86_CPU_HAS_SSE2

	select BR2_X86_CPU_HAS_SSE3

	depends on !BR2_x86_64

config BR2_x86_nocona

	bool "nocona"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	select BR2_X86_CPU_HAS_SSE2

	select BR2_X86_CPU_HAS_SSE3

config BR2_x86_core2

	bool "core2"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	select BR2_X86_CPU_HAS_SSE2

	select BR2_X86_CPU_HAS_SSE3

	select BR2_X86_CPU_HAS_SSSE3

config BR2_x86_atom

	bool "atom"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	select BR2_X86_CPU_HAS_SSE2

	select BR2_X86_CPU_HAS_SSE3

	select BR2_X86_CPU_HAS_SSSE3

config BR2_x86_k6

	bool "k6"

	select BR2_X86_CPU_HAS_MMX

	depends on !BR2_x86_64

config BR2_x86_k6_2

	bool "k6-2"

	select BR2_X86_CPU_HAS_MMX

	depends on !BR2_x86_64

config BR2_x86_athlon

	bool "athlon"

	select BR2_X86_CPU_HAS_MMX

	depends on !BR2_x86_64

config BR2_x86_athlon_4

	bool "athlon-4"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	depends on !BR2_x86_64

config BR2_x86_opteron

	bool "opteron"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	select BR2_X86_CPU_HAS_SSE2

config BR2_x86_opteron_sse3

	bool "opteron w/ SSE3"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	select BR2_X86_CPU_HAS_SSE2

	select BR2_X86_CPU_HAS_SSE3

config BR2_x86_barcelona

	bool "barcelona"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	select BR2_X86_CPU_HAS_SSE2

	select BR2_X86_CPU_HAS_SSE3

config BR2_x86_geode

	bool "geode"

	# Don't include MMX support because there several variant of geode

	# processor, some with MMX support, some without.

	# See: http://en.wikipedia.org/wiki/Geode_%28processor%29

	depends on !BR2_x86_64

config BR2_x86_c3

	bool "Via/Cyrix C3 (Samuel/Ezra cores)"

	select BR2_X86_CPU_HAS_MMX

	depends on !BR2_x86_64

config BR2_x86_c32

	bool "Via C3-2 (Nehemiah cores)"

	select BR2_X86_CPU_HAS_MMX

	select BR2_X86_CPU_HAS_SSE

	depends on !BR2_x86_64

config BR2_x86_winchip_c6

	bool "IDT Winchip C6"

	select BR2_X86_CPU_HAS_MMX

	depends on !BR2_x86_64

config BR2_x86_winchip2

	bool "IDT Winchip 2"

	select BR2_X86_CPU_HAS_MMX

	depends on !BR2_x86_64

endchoice



choice

	prompt "Target Architecture Variant"

	depends on BR2_sparc

	default BR2_sparc_v7

	help

	  Specific CPU variant to use



config BR2_sparc_v7

	bool "v7"

config BR2_sparc_cypress

	bool "cypress"

config BR2_sparc_v8

	bool "v8"

config BR2_sparc_sparchfleon

	bool "hfleon"

config BR2_sparc_sparchfleonv8

	bool "hfleonv8"

config BR2_sparc_sparcsfleon

	bool "sfleon"

config BR2_sparc_sparcsfleonv8

	bool "sfleonv8"

config BR2_sparc_supersparc

	bool "supersparc"

config BR2_sparc_sparclite

	bool "sparclite"

config BR2_sparc_f930

	bool "f930"

config BR2_sparc_f934

	bool "f934"

config BR2_sparc_hypersparc

	bool "hypersparc"

config BR2_sparc_sparclite86x

	bool "sparclite86x"

config BR2_sparc_sparclet

	bool "sparclet"

config BR2_sparc_tsc701

	bool "tsc701"

endchoice



choice

	prompt "Target Architecture Variant"

	depends on BR2_powerpc

	default BR2_generic_powerpc

	help

	  Specific CPU variant to use

config BR2_generic_powerpc

	bool "generic"

config BR2_powerpc_401

	bool "401"

config BR2_powerpc_403

	bool "403"

config BR2_powerpc_405

	bool "405"

config BR2_powerpc_405fp

	bool "405 with FPU"

config BR2_powerpc_440

	bool "440"

config BR2_powerpc_440fp

	bool "440 with FPU"

config BR2_powerpc_505

	bool "505"

config BR2_powerpc_601

	bool "601"

config BR2_powerpc_602

	bool "602"

config BR2_powerpc_603

	bool "603"

config BR2_powerpc_603e

	bool "603e"

config BR2_powerpc_604

	bool "604"

config BR2_powerpc_604e

	bool "604e"

config BR2_powerpc_620

	bool "620"

config BR2_powerpc_630

	bool "630"

config BR2_powerpc_740

	bool "740"

config BR2_powerpc_7400

	bool "7400"

config BR2_powerpc_7450

	bool "7450"

config BR2_powerpc_750

	bool "750"

config BR2_powerpc_801

	bool "801"

config BR2_powerpc_821

	bool "821"

config BR2_powerpc_823

	bool "823"

config BR2_powerpc_860

	bool "860"

config BR2_powerpc_970

	bool "970"

config BR2_powerpc_8540

	bool "8540 / e500v1"

config BR2_powerpc_8548

	bool "8548 / e500v2"

config BR2_powerpc_e300c2

	bool "e300c2"

config BR2_powerpc_e300c3

	bool "e300c3"

config BR2_powerpc_e500mc

	bool "e500mc"

endchoice



choice

	prompt "Target ABI"

	depends on BR2_powerpc

	default BR2_powerpc_SPE if BR2_powerpc_8540 || BR2_powerpc_8548

	default BR2_powerpc_CLASSIC

	help

	  Application Binary Interface to use



config BR2_powerpc_CLASSIC

	bool "Classic"

	depends on !(BR2_powerpc_8540 || BR2_powerpc_8548)

config BR2_powerpc_SPE

	bool "SPE"

	depends on BR2_powerpc_8540 || BR2_powerpc_8548

endchoice



config BR2_ARCH

	string

	default "arm"		if BR2_arm