u-boot: remove arch specific patches infrastructure (1cee7b34) · Commits · Dom Sekotill / buildroot

boot/u-boot/Config.in

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Original line number	Diff line number	Diff line
		@@ -33,8 +33,6 @@ config BR2_UBOOT_VERSION
		default "2009.11" if BR2_TARGET_UBOOT_2009_11
		default "2009.08" if BR2_TARGET_UBOOT_2009_08

		source "target/device/Config.in.u-boot"

		config BR2_TARGET_UBOOT_CUSTOM_PATCH
		string "custom patch"
		help

target/device/Atmel/arch-arm/Makefile.in

deleted100644 → 0

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Original line number	Diff line number	Diff line
		include target/device/Atmel/arch-arm/u-boot/Makefile.in

target/device/Atmel/arch-arm/u-boot/2009.01/u-boot-2009.01-001-at91rm9200.patch

deleted100644 → 0

+0 −723

File deleted.

Preview size limit exceeded, changes collapsed.

target/device/Atmel/arch-arm/u-boot/2009.01/u-boot-2009.01-002-at91rm9200dk.h.patch

deleted100644 → 0

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Original line number	Diff line number	Diff line
		diff -urN u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk_df.h u-boot-2009.01/include/configs/at91rm9200dk_df.h
		--- u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk_df.h 1970-01-01 01:00:00.000000000 +0100
		+++ u-boot-2009.01/include/configs/at91rm9200dk_df.h 2009-01-01 21:19:30.000000000 +0100
		@@ -0,0 +1,251 @@
		+/*
		+ * Rick Bronson <rick@efn.org>
		+ *
		+ * Configuration settings for the AT91RM9200DK board.
		+ *
		+ * See file CREDITS for list of people who contributed to this
		+ * project.
		+ *
		+ * This program is free software; you can redistribute it and/or
		+ * modify it under the terms of the GNU General Public License as
		+ * published by the Free Software Foundation; either version 2 of
		+ * the License, or (at your option) any later version.
		+ *
		+ * This program is distributed in the hope that it will be useful,
		+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
		+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		+ * GNU General Public License for more details.
		+ *
		+ * You should have received a copy of the GNU General Public License
		+ * along with this program; if not, write to the Free Software
		+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
		+ * MA 02111-1307 USA
		+ */
		+
		+#ifndef __CONFIG_H
		+#define __CONFIG_H
		+#define AT91RM9200_BOARD MACH_TYPE_AT91RM9200DK
		+#define CONFIG_HOSTNAME at91rm9200dk
		+
		+/* ARM asynchronous clock */
		+#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
		+#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
		+/* #define AT91C_MASTER_CLOCK 44928000 / / peripheral clock (AT91C_MASTER_CLOCK / 4) */
		+
		+#define AT91_SLOW_CLOCK 32768 /* slow clock */
		+
		+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
		+#define CONFIG_AT91 1 /* THis is an ARM from the AT91 family */
		+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
		+#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
		+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
		+#define USE_920T_MMU 1
		+
		+#define CONFIG_SKIP_LOWLEVEL_INIT /* Already done by dataflashboot */
		+
		+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
		+#define CONFIG_SETUP_MEMORY_TAGS 1
		+#define CONFIG_INITRD_TAG 1
		+
		+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
		+#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
		+/* flash */
		+#define MC_PUIA_VAL 0x00000000
		+#define MC_PUP_VAL 0x00000000
		+#define MC_PUER_VAL 0x00000000
		+#define MC_ASR_VAL 0x00000000
		+#define MC_AASR_VAL 0x00000000
		+#define EBI_CFGR_VAL 0x00000000
		+#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
		+
		+/* clocks */
		+#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
		+#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
		+#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
		+
		+/* sdram */
		+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
		+#define PIOC_BSR_VAL 0x00000000
		+#define PIOC_PDR_VAL 0xFFFF0000
		+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
		+#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
		+#define SDRAM 0x20000000 /* address of the SDRAM */
		+#define SDRAM1 0x20000080 /* address of the SDRAM */
		+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
		+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
		+#define SDRC_MR_VAL1 0x00000004 /* refresh */
		+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
		+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
		+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
		+#else
		+#define CONFIG_SKIP_RELOCATE_UBOOT
		+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
		+/*
		+ * Size of malloc() pool
		+ */
		+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
		+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
		+
		+#define CONFIG_BAUDRATE 115200
		+
		+/*
		+ * Hardware drivers
		+ */
		+
		+/* define one of these to choose the DBGU, USART0 or USART1 as console */
		+#define CONFIG_DBGU
		+#undef CONFIG_USART0
		+#undef CONFIG_USART1
		+
		+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
		+
		+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
		+
		+#define CONFIG_BOOTDELAY 3
		+/* #define CONFIG_ENV_OVERWRITE 1 */
		+
		+
		+/*
		+ * BOOTP options
		+ */
		+#define CONFIG_BOOTP_BOOTFILESIZE
		+#define CONFIG_BOOTP_BOOTPATH
		+#define CONFIG_BOOTP_GATEWAY
		+#define CONFIG_BOOTP_HOSTNAME
		+
		+
		+/*
		+ * Command line configuration.
		+ */
		+#include <config_cmd_default.h>
		+
		+#define CONFIG_CMD_DHCP
		+#define CONFIG_CMD_MII
		+#define CONFIG_CMD_NAND
		+#define CONFIG_CMD_AT91_SPIMUX
		+
		+#define CONFIG_NAND_LEGACY
		+
		+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
		+#define SECTORSIZE 512
		+
		+#define ADDR_COLUMN 1
		+#define ADDR_PAGE 2
		+#define ADDR_COLUMN_PAGE 3
		+
		+#define NAND_ChipID_UNKNOWN 0x00
		+#define NAND_MAX_FLOORS 1
		+#define NAND_MAX_CHIPS 1
		+
		+#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
		+#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
		+
		+#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
		+#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
		+#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
		+
		+#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
		+
		+#define WRITE_NAND_COMMAND(d, adr) do{ (volatile __u8 )((unsigned long)adr \| AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
		+#define WRITE_NAND_ADDRESS(d, adr) do{ (volatile __u8 )((unsigned long)adr \| AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
		+#define WRITE_NAND(d, adr) do{ (volatile __u8 )((unsigned long)adr) = (__u8)d; } while(0)
		+#define READ_NAND(adr) ((volatile unsigned char)((volatile __u8 )(unsigned long)adr))
		+/* the following are NOP's in our implementation */
		+#define NAND_CTL_CLRALE(nandptr)
		+#define NAND_CTL_SETALE(nandptr)
		+#define NAND_CTL_CLRCLE(nandptr)
		+#define NAND_CTL_SETCLE(nandptr)
		+
		+#define CONFIG_NR_DRAM_BANKS 1
		+#define PHYS_SDRAM 0x20000000
		+#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
		+
		+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
		+#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
		+
		+#define CONFIG_DRIVER_ETHER
		+#define CONFIG_NET_RETRY_COUNT 20
		+#define CONFIG_AT91C_USE_RMII
		+
		+/* AC Characteristics */
		+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
		+#define DATAFLASH_TCSS (0xC << 16)
		+#define DATAFLASH_TCHS (0x1 << 24)
		+
		+#define CONFIG_HAS_DATAFLASH 1
		+#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
		+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
		+#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
		+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
		+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
		+#define CONFIG__SUPPORT_BLOCK_ERASE 1
		+
		+
		+#define PHYS_FLASH_1 0x10000000
		+#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
		+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
		+#define CONFIG_SYS_MAX_FLASH_BANKS 1
		+#define CONFIG_SYS_MAX_FLASH_SECT 256
		+#define CONFIG_SYS_FLASH_ERASE_TOUT (2CONFIG_SYS_HZ) / Timeout for Flash Erase */
		+#define CONFIG_SYS_FLASH_WRITE_TOUT (2CONFIG_SYS_HZ) / Timeout for Flash Write */
		+
		+#define CONFIG_ENV_IS_IN_DATAFLASH 1
		+#define CONFIG_NEW_PARTITION 1
		+
		+#ifdef CONFIG_ENV_IS_IN_DATAFLASH
		+#ifdef CONFIG_NEW_PARTITION
		+#define CONFIG_ENV_OFFSET 0x4200
		+#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
		+#define CONFIG_ENV_SIZE 0x2000 /* 8 * 1056 really , but start.s is not OK with this*/
		+#else
		+#define CONFIG_ENV_OFFSET 0x20000
		+#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
		+#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
		+#endif
		+#else
		+#define CONFIG_ENV_IS_IN_FLASH 1
		+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
		+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
		+#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
		+#else
		+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
		+#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
		+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
		+#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
		+
		+#if defined(CONFIG_AT91RM9200DK)
		+#define DATAFLASH_MMC_SELECT AT91_PIN_PB7
		+#else
		+#define DATAFLASH_MMC_SELECT AT91_PIN_PB22
		+#endif
		+
		+#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
		+
		+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
		+#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
		+#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
		+#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
		+#else
		+#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
		+#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
		+#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
		+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
		+
		+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
		+
		+#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
		+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
		+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
		+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
		+
		+#define CONFIG_SYS_HZ 1000
		+#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
		+ /* AT91C_TC_TIMER_DIV1_CLOCK */
		+
		+#define CONFIG_STACKSIZE (321024) / regular stack */
		+
		+#ifdef CONFIG_USE_IRQ
		+#error CONFIG_USE_IRQ not supported
		+#endif
		+
		+#endif
		diff -urN u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk.h u-boot-2009.01/include/configs/at91rm9200dk.h
		--- u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk.h 2009-01-01 13:09:35.000000000 +0100
		+++ u-boot-2009.01/include/configs/at91rm9200dk.h 2009-01-01 17:06:32.000000000 +0100
		@@ -24,6 +24,8 @@

		#ifndef __CONFIG_H
		#define __CONFIG_H
		+#define AT91RM9200_BOARD MACH_TYPE_AT91RM9200DK
		+#define CONFIG_HOSTNAME at91rm9200dk

		/* ARM asynchronous clock */
		#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
		@@ -33,6 +35,7 @@
		#define AT91_SLOW_CLOCK 32768 /* slow clock */

		#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
		+#define CONFIG_AT91 1 /* THis is an ARM from the AT91 family */
		#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
		#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
		#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
		@@ -117,6 +120,7 @@
		#define CONFIG_CMD_DHCP
		#define CONFIG_CMD_MII
		#define CONFIG_CMD_NAND
		+#define CONFIG_CMD_AT91_SPIMUX

		#define CONFIG_NAND_LEGACY

		@@ -198,6 +202,11 @@
		#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
		#endif /* CONFIG_ENV_IS_IN_DATAFLASH */

		+#if defined(CONFIG_AT91RM9200DK)
		+#define DATAFLASH_MMC_SELECT AT91_PIN_PB7
		+#else
		+#define DATAFLASH_MMC_SELECT AT91_PIN_PB22
		+#endif

		#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */

		diff -urN u-boot-2009.01-rc1-0rig//Makefile u-boot-2009.01/Makefile
		--- u-boot-2009.01-rc1-0rig//Makefile 2009-01-01 13:09:30.000000000 +0100
		+++ u-boot-2009.01/Makefile 2009-01-01 21:35:24.000000000 +0100
		@@ -2562,6 +2562,9 @@
		## Atmel AT91RM9200 Systems
		#########################################################################

		+at91rm9200dk_df_config : unconfig
		+ @$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
		+
		at91rm9200dk_config : unconfig
		@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200

target/device/Atmel/arch-arm/u-boot/2009.01/u-boot-2009.01-003-at91rm9200dk.patch

deleted100644 → 0

+0 −324

Original line number	Diff line number	Diff line
		diff -urN u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/at91rm9200dk.c u-boot-2009.01/board/atmel/at91rm9200dk/at91rm9200dk.c
		--- u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/at91rm9200dk.c 2009-01-01 13:09:31.000000000 +0100
		+++ u-boot-2009.01/board/atmel/at91rm9200dk/at91rm9200dk.c 2009-01-01 16:11:36.000000000 +0100
		@@ -3,6 +3,9 @@
		* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
		* Marius Groeger <mgroeger@sysgo.de>
		*
		+ * (C) Copyright 2008
		+ * Ulf Samuelsson <ulf.samuelsson@atmel.com>
		+ *
		* See file CREDITS for list of people who contributed to this
		* project.
		*
		@@ -24,6 +27,10 @@

		#include <common.h>
		#include <asm/arch/AT91RM9200.h>
		+#include <asm/arch/at91_pmc.h>
		+#include <asm/arch/at91_pio.h>
		+#include <asm/arch/gpio.h>
		+#include <asm/arch/io.h>
		#include <at91rm9200_net.h>
		#include <dm9161.h>

		@@ -41,13 +48,13 @@

		/* Correct IRDA resistor problem */
		/* Set PA23_TXD in Output */
		- ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
		+ at91_set_gpio_output(AT91_PIN_PA23, 1);

		/* memory and cpu-speed are setup before relocation */
		/* so we do _nothing_ here */

		/* arch number of AT91RM9200DK-Board */
		- gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200DK;
		+ gd->bd->bi_arch_number = AT91RM9200_BOARD;
		/* adress of boot parameters */
		gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

		@@ -91,46 +98,58 @@
		*/
		#if defined(CONFIG_CMD_NAND)
		extern ulong nand_probe (ulong physadr);
		+/* set the bus interface characteristics based on
		+ * tDS Data Set up Time 30 - ns
		+ * tDH Data Hold Time 20 - ns
		+ * tALS ALE Set up Time 20 - ns
		+ * 16ns at 60 MHz ~= 3
		+ */

		-#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
		-void nand_init (void)
		-{
		- /* Setup Smart Media, fitst enable the address range of CS3 */
		- *AT91C_EBI_CSA \|= AT91C_EBI_CS3A_SMC_SmartMedia;
		- /* set the bus interface characteristics based on
		- tDS Data Set up Time 30 - ns
		- tDH Data Hold Time 20 - ns
		- tALS ALE Set up Time 20 - ns
		- 16ns at 60 MHz ~= 3 */
		/memory mapping structures /
		#define SM_ID_RWH (5 << 28)
		#define SM_RWH (1 << 28)
		#define SM_RWS (0 << 24)
		#define SM_TDF (1 << 8)
		#define SM_NWS (3)
		- AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH \| SM_RWS \|
		- AT91C_SMC2_ACSS_STANDARD \| AT91C_SMC2_DBW_8 \|
		- SM_TDF \| AT91C_SMC2_WSEN \| SM_NWS);
		+
		+#define SMARTMEDIA_INIT ( \
		+ SM_RWH \| \
		+ SM_RWS \| \
		+ AT91C_SMC2_ACSS_STANDARD \| \
		+ AT91C_SMC2_DBW_8 \| \
		+ SM_TDF \| \
		+ AT91C_SMC2_WSEN \| \
		+ SM_NWS \
		+ )
		+
		+
		+
		+#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
		+void nand_init (void)
		+{
		+ /* Setup Smart Media, fitst enable the address range of CS3 */
		+ /* AT91C_EBI_CSA \|= AT91C_EBI_CS3A_SMC_SmartMedia; /
		+ at91_sys_setbit(AT91C_EBI_CS3A_SMC_SmartMedia, AT91_EBI_CSA);
		+
		+ /* Init Smartmedia Interface */
		+ at91_sys_write(AT91_SMC2_CSR3, SMARTMEDIA_INIT);

		/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
		- *AT91C_PIOC_ASR = AT91C_PC0_BFCK \| AT91C_PC1_BFRDY_SMOE \|
		- AT91C_PC3_BFBAA_SMWE;
		- *AT91C_PIOC_PDR = AT91C_PC0_BFCK \| AT91C_PC1_BFRDY_SMOE \|
		- AT91C_PC3_BFBAA_SMWE;
		+ at91_set_A_periph(AT91_PIN_PC0, 0); /* BFCK */
		+ at91_set_A_periph(AT91_PIN_PC1, 0); /* BFRDY/SMOE */
		+ at91_set_A_periph(AT91_PIN_PC3, 0); /* BFBAA/SMWE */

		/* Configure PC2 as input (signal READY of the SmartMedia) */
		- AT91C_PIOC_PER = AT91C_PC2_BFAVD; / enable direct output enable */
		- AT91C_PIOC_ODR = AT91C_PC2_BFAVD; / disable output */
		+ at91_set_gpio_input(AT91_PIN_PC2, 0);

		/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
		- AT91C_PIOB_PER = AT91C_PIO_PB1; / enable direct output enable */
		- AT91C_PIOB_ODR = AT91C_PIO_PB1; / disable output */
		+ at91_set_gpio_input(AT91_PIN_PB1, 0);

		/* PIOB and PIOC clock enabling */
		- *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
		- *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
		+ at91_sys_write(AT91_PMC_PCER, 1 << AT91RM9200_ID_PIOB);
		+ at91_sys_write(AT91_PMC_PCER, 1 << AT91RM9200_ID_PIOC);

		- if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
		+ if (at91_get_gpio_value(AT91_PIN_PB1))
		printf (" No SmartMedia card inserted\n");
		#ifdef DEBUG
		printf (" SmartMedia card inserted\n");
		@@ -140,3 +159,4 @@
		printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
		}
		#endif
		+
		diff -urN u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/led.c u-boot-2009.01/board/atmel/at91rm9200dk/led.c
		--- u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/led.c 2009-01-01 13:09:31.000000000 +0100
		+++ u-boot-2009.01/board/atmel/at91rm9200dk/led.c 2009-01-01 15:53:56.000000000 +0100
		@@ -24,57 +24,105 @@

		#include <common.h>
		#include <asm/arch/AT91RM9200.h>
		+/#include <asm/arch/at91_pmc.h>/
		+#include <asm/arch/gpio.h>
		+#include <asm/arch/io.h>

		-#define GREEN_LED AT91C_PIO_PB0
		-#define YELLOW_LED AT91C_PIO_PB1
		-#define RED_LED AT91C_PIO_PB2
		+#define GREEN_LED AT91_PIN_PB0
		+#define YELLOW_LED AT91_PIN_PB1
		+#define RED_LED AT91_PIN_PB2

		-void green_LED_on(void)
		+
		+#define GREEN_LED_ON 0
		+#define GREEN_LED_OFF 1
		+#define YELLOW_LED_ON 0
		+#define YELLOW_LED_OFF 1
		+#define RED_LED_ON 0
		+#define RED_LED_OFF 1
		+
		+#define TIME_SLICE 500000
		+
		+void yellow_LED_on(void)
		+{
		+ at91_set_gpio_value(YELLOW_LED, YELLOW_LED_ON);
		+}
		+
		+void yellow_LED_off(void)
		+{
		+ at91_set_gpio_value(YELLOW_LED, YELLOW_LED_OFF);
		+}
		+
		+void red_LED_on(void)
		{
		- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
		- PIOB->PIO_CODR = GREEN_LED;
		+ at91_set_gpio_value(RED_LED, RED_LED_ON);
		}

		-void yellow_LED_on(void)
		+void red_LED_off(void)
		{
		- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
		- PIOB->PIO_CODR = YELLOW_LED;
		+ at91_set_gpio_value(RED_LED, RED_LED_OFF);
		}

		-void red_LED_on(void)
		+void green_LED_on(void)
		{
		- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
		- PIOB->PIO_CODR = RED_LED;
		+ at91_set_gpio_value(GREEN_LED, GREEN_LED_ON);
		}

		-void green_LED_off(void)
		+void green_LED_off(void)
		{
		- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
		- PIOB->PIO_SODR = GREEN_LED;
		+ at91_set_gpio_value(GREEN_LED, GREEN_LED_OFF);
		}

		-void yellow_LED_off(void)
		+static void delay(unsigned int time)
		{
		- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
		- PIOB->PIO_SODR = YELLOW_LED;
		+ volatile unsigned int counter = time;
		+ while(counter > 0) counter--;
		}

		-void red_LED_off(void)
		+void green_LED_blink(unsigned int time)
		{
		- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
		- PIOB->PIO_SODR = RED_LED;
		+ while(time > 0) {
		+ green_LED_on();
		+ delay(TIME_SLICE);
		+ green_LED_off();
		+ delay(TIME_SLICE);
		+ time--;
		+ }
		}

		+void yellow_LED_blink(unsigned int time)
		+{
		+ while(time > 0) {
		+ yellow_LED_on();
		+ delay(TIME_SLICE);
		+ yellow_LED_off();
		+ delay(TIME_SLICE);
		+ time--;
		+ }
		+}

		-void coloured_LED_init (void)
		+void red_LED_blink(unsigned int time)
		{
		- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
		- AT91PS_PMC PMC = AT91C_BASE_PMC;
		- PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Enable PIOB clock */
		- /* Disable peripherals on LEDs */
		- PIOB->PIO_PER = AT91C_PIO_PB2 \| AT91C_PIO_PB1 \| AT91C_PIO_PB0;
		- /* Enable pins as outputs */
		- PIOB->PIO_OER = AT91C_PIO_PB2 \| AT91C_PIO_PB1 \| AT91C_PIO_PB0;
		- /* Turn all LEDs OFF */
		- PIOB->PIO_SODR = AT91C_PIO_PB2 \| AT91C_PIO_PB1 \| AT91C_PIO_PB0;
		+ while(time > 0) {
		+ red_LED_on();
		+ delay(TIME_SLICE);
		+ red_LED_off();
		+ delay(TIME_SLICE);
		+ time--;
		+ }
		}
		+
		+void coloured_LED_init(void)
		+{
		+ /* Enable clock */
		+ at91_sys_write(AT91C_PMC_PCER, 1 << AT91RM9200_ID_PIOB);
		+
		+ at91_set_gpio_output(GREEN_LED, 1);
		+ at91_set_gpio_output(YELLOW_LED, 1);
		+ at91_set_gpio_output(RED_LED, 1);
		+
		+ at91_set_gpio_value(GREEN_LED, GREEN_LED_OFF);
		+ at91_set_gpio_value(YELLOW_LED, YELLOW_LED_OFF);
		+ at91_set_gpio_value(RED_LED, RED_LED_ON);
		+}
		+
		+
		diff -urN u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/mux.c u-boot-2009.01/board/atmel/at91rm9200dk/mux.c
		--- u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/mux.c 2009-01-01 13:09:31.000000000 +0100
		+++ u-boot-2009.01/board/atmel/at91rm9200dk/mux.c 2009-01-01 16:38:01.000000000 +0100
		@@ -1,37 +1,29 @@
		#include <config.h>
		#include <common.h>
		#include <asm/hardware.h>
		+#include <asm/arch/at91_pio.h>
		+#include <asm/arch/gpio.h>
		+#include <asm/arch/io.h>
		#include <dataflash.h>

		int AT91F_GetMuxStatus(void) {
		-#ifdef DATAFLASH_MMC_SELECT
		- AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
		- AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
		-
		-
		- if(AT91C_BASE_PIOB->PIO_ODSR & DATAFLASH_MMC_SELECT) {
		- return 1;
		- } else {
		- return 0;
		- }
		-#endif
		+#ifdef CONFIG_CMD_AT91_SPIMUX
		+ return at91_get_gpio_value(DATAFLASH_MMC_SELECT);
		+#else
		return 0;
		+#endif
		}

		-void AT91F_SelectMMC(void) {
		-#ifdef DATAFLASH_MMC_SELECT
		- AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
		- AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
		- /* Set Output */
		- AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT;
		+void AT91F_SelectMMC(void)
		+{
		+#ifdef CONFIG_CMD_AT91_SPIMUX
		+ at91_set_gpio_output(DATAFLASH_MMC_SELECT, 1); /* Set in PIO mode and select SD-Card*/
		#endif
		}

		void AT91F_SelectSPI(void) {
		-#ifdef DATAFLASH_MMC_SELECT
		- AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
		- AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
		- /* Clear Output */
		- AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT;
		+#ifdef CONFIG_CMD_AT91_SPIMUX
		+ at91_set_gpio_output(DATAFLASH_MMC_SELECT, 0); /* Set in PIO mode and select SPI */
		#endif
		}
		+